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FEATURES 16-Bit Sigma-Delta ADC 468.75 kHz Output Word Rate (OWR) No Missing Codes Low-Pass Digital Filter High Speed Serial Interface Linear Phase 229.2 kHz Input Bandwidth Power Supplies: AVDD, DVDD: +5 V 5% Standby Mode (70 W) Parallel Mode (12-Bit/312.5 kHz OWR)
CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC AD7721
FUNCTIONAL BLOCK DIAGRAM
AGND DGND DGND DSUBST VIN1 VIN2 DVAL/SYNC CS RD WR DRDY SDATA/DB11 CONTROL LOGIC RFS/DB10 DB9 CLK AGND AVDD DVDD
AD7721
12-BIT A/D CONVERTER MODULATOR FIR FILTER REFIN
STBY/DB0 CAL/DB1 UNI/DB2
GENERAL DESCRIPTION
The AD7721 is a complete low power, 12-/16-bit, sigma-delta ADC. The part operates from a +5 V supply and accepts a differential input of 0 V to 2.5 V or 1.25 V. The analog input is continuously sampled by an analog modulator at twice the clock frequency eliminating the need for external sample-andhold circuitry. The modulator output is processed by two finite impulse response (FIR) digital filters in series. The on-chip filtering reduces the external antialias requirements to first order in most cases. Settling time for a step input is 97.07 s while the group delay for the filter is 48.53 s when the master clock equals 15 MHz. The AD7721 can be operated with input bandwidths up to 229.2 kHz. The corresponding output word rate is 468.75 kHz. The part can be operated with lower clock frequencies also. The sample rate, filter corner frequency and output word rate will be reduced also, as these are proportional to the external clock frequency. The maximum clock frequencies in parallel mode and serial mode are 10 MHz and 15 MHz respectively.
DB3
DB4
SYNC/ DB6 DB5
SCLK/ DB8 DB7
Use of a single bit DAC in the modulator guarantees excellent linearity and dc accuracy. Endpoint accuracy is ensured by onchip calibration of offset and gain. This calibration procedure minimizes the part's zero-scale and full-scale errors. The output data is accessed from the output register through a serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors. The serial interface operates in internal clocking (master) mode, the AD7721 providing the serial clock. CMOS construction ensures low power dissipation while a power-down mode reduces the power consumption to only 100 W.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997
5%; = DGND = 0 V, AD7721-SPECIFICATIONS1 (AV = =15+5 V REFIN DV+2.5+5 TV = T5%;toAGND ,=unless otherwise noted) f MHz, = V; T
DD DD CLK A MIN MAX
Parameter SERIAL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error2 Unipolar Mode Bipolar Mode Full-Scale Error 2, 3 Unipolar Mode Bipolar Mode Unipolar Offset Drift Bipolar Offset Drift ANALOG INPUTS Signal Input Span (VIN1-VIN2) Bipolar Mode Unipolar Mode Maximum Input Voltage Minimum Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance REFERENCE INPUTS VREFIN REFIN Input Current DYNAMIC SPECIFICATIONS Signal to (Noise + Distortion) Total Harmonic Distortion Frequency Response 0 kHz-210 kHz 229.2 kHz 259.01 kHz to 14.74 MHz CLOCK CLK Duty Ratio VCLKH, CLK High Voltage VCLKL, CLK Low Voltage LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD IDD (Total from AVDD, DVDD) Power Consumption Power Consumption
A Version
S Version
Units
Test Conditions/Comments
16 12 8 16 70 3.66 3.66 4.88 4.88 0.05 0.04
16 12 8 16 70 3.66 3.66 4.88 4.88 0.05 0.04
Bits Bits min LSB typ LSB max dB min mV max mV max mV max mV max mV/C typ mV/C typ
Guaranteed 12 Bits Monotonic
16-Bit Operation Bipolar Mode Typically 0.61 mV Typically 0.61 mV Typically 0.61 mV Typically 1.22 mV
VREFIN/2 0 to VREFIN AVDD 0 1.6 2 fCLK 20.8 2.4 to 2.6 200 74 -78 0.05 -3 -72 45 to 55 0.7 x DVDD 0.3 x DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
VREFIN/2 0 to VREFIN AVDD 0 1.6 2 fCLK 20.8 2.4 to 2.6 200 74 -78 0.05 -3 -72 45 to 55 0.7 x DVDD 0.3 x DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
Volts max Volts max Volts Volts pF typ MHz k typ V min/V max A typ dB min dB max dB max dB min dB min % max V min V max V min V max A max pF max V min V max V min/V max V min/V max mA max mW max W max
UNI = VIH UNI = VIL
Guaranteed by Design With 15 MHz on CLK Pin
Input Bandwidth 0 kHz to 210 kHz Input Bandwidth 0 kHz to 229.2 kHz
For Specified Operation CLK Uses CMOS Logic
|IOUT| 200 A |IOUT| 1.6 mA
Digital Inputs Equal to 0 V or DVDD Active Mode Standby Mode
NOTES 1 Operating temperature range is as follows: A Version: -40C to +85C; S Version: -55C to +125C. 2 Applies after calibration at temperature of interest. 3 Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin. Specifications subject to change without notice.
-2-
REV. A
SPECIFICATIONS1 (AV ==+5 V V;5%;=DV REFIN +2.5 T T
DD A
= +5 V 5%; AGND = DGND = 0 V, fCLK = 10 MHz, to TMAX, unless otherwise noted) MIN
DD
AD7721
Parameter PARALLEL MODE ONLY STATIC PERFORMANCE Resolution Minimum Resolution for Which No Missing Codes Is Guaranteed Differential Nonlinearity Integral Nonlinearity DC CMRR Offset Error2 Unipolar Mode Bipolar Mode Full-Scale Error 2, 3 Unipolar Mode Bipolar Mode Unipolar Offset Drift Bipolar Offset Drift ANALOG INPUTS Signal Input Span (VIN1-VIN2): Bipolar Mode Unipolar Mode Maximum Input Voltage Minimum Input Voltage Input Sampling Capacitance Input Sampling Rate Differential Input Impedance REFERENCE INPUTS VREFIN REFIN Input Current DYNAMIC SPECIFICATIONS Signal to (Noise + Distortion) Total Harmonic Distortion Frequency Response 0 kHz-140 kHz 152.8 kHz 172.67 kHz to 9.827 MHz CLOCK CLK Duty Ratio VCLKH, CLK High Voltage VCLKL, CLK Low Voltage LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL , Output Low Voltage POWER SUPPLIES AVDD DVDD IDD (Total from AVDD, DVDD) Power Consumption Power Consumption
A Version
S Version
Units
Test Conditions/Comments
12 12 1/2 1/2 70 3.66 3.66 4.88 4.88 0.04 0.035
12 12 1/2 1/2 70 3.66 3.66 4.88 4.88 0.04 0.035
Bits Bits min LSB typ LSB typ dB min mV max mV max mV max mV max mV/C typ mV/C typ
Guaranteed 12 Bits Monotonic 12-Bit Operation Bipolar Mode Typically 0.61 mV Typically 0.61 mV Typically 0.61 mV Typically 1.22 mV
VREFIN/2 0 to VREFIN AVDD 0 1.6 2 fCLK 31.25 2.4 to 2.6 200 70 -78 0.05 -3 -72 45 to 55 0.7 x DVDD 0.3 x DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
VREFIN/2 0 to VREFIN AVDD 0 1.6 2 fCLK 31.25 2.4 to 2.6 200 70 -78 0.05 -3 -72 45 to 55 0.7 x DVDD 0.3 x DVDD 2.0 0.8 10 10 4.0 0.4 4.75/5.25 4.75/5.25 28.5 150 100
Volts max Volts max Volts Volts pF typ MHz k typ V min/V max A typ dB min dB max dB max dB min dB min % max V min V max V min V max A max pF max V min V max V min/V max V min/V max mA max mW max W max
UNI = VIH UNI = VIL
Guaranteed by Design With 10 MHz on CLK Pin
Input Bandwidth 0 kHz to 140 kHz Input Bandwidth 0 kHz to 152.8 kHz
For Specified Operation CLK Uses CMOS Logic
|IOUT| 200 A |IOUT| 1.6 mA
Digital Inputs Equal to 0 V or DVDD
Active Mode Standby Mode
NOTES 1 Operating temperature range is as follows: A Version: -40C to +85C; S Version: -55C to +125C. 2 Applies after calibration at temperature of interest. 3 Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin. Specifications subject to change without notice.
REV. A
-3-
AD7721 TIMING CHARACTERISTICS1, 2
Parameter Serial Interface fCLK3 tCLK LO tCLK HI t1 t2 4 t3 t4 t5 t6 t7 t8 5 t9 Parallel Interface fCLK3 tCLK LO tCLK HI Read Operation t10 t11 t12 Write Operation t13 t14 t15
(AVDD= +5 V 5%; DVDD= +5 V unless otherwise noted)
Units kHz min MHz max ns min ns min ns nom ns min ns max ns nom ns nom ns max ns min ns min ns max ns nom kHz min MHz max ns min ns min ns nom ns max ns nom ns min ns min ns min
5%; AGND = DGND = 0 V, REFIN = +2.5 V
Limit at TMIN, TMAX (A, S Versions) 100 15 0.45 x tCLK 0.45 x tCLK tCLK tCLK HI - 10 20 tCLK HI tCLK LO 25 0 0 20 32 x tCLK 100 10 0.45 x tCLK 0.45 x tCLK 2 x tCLK 30 32 x tCLK 35 20 0
Conditions/Comments Master Clock Frequency 15 MHz for Specified Performance Master Clock Input Low Time Master Clock Input High Time DRDY High Time RFS Low to SCLK Falling Edge Setup Time RFS Low to Data Valid Delay SCLK High Pulse Width SCLK Low Pulse Width SCLK Rising Edge to Data Valid Delay RFS to SCLK Falling Edge Hold Time Bus Relinquish Time after Rising Edge of RFS Period between Consecutive DRDY Rising Edges Master Clock Frequency 10 MHz for Specified Performance Master Clock Input Low Time Master Clock Input High Time DRDY High Time Data Access Time after Falling Edge of DRDY Period between Consecutive DRDY Rising Edges WR Pulse Width Data Valid to WR High Setup Time Data Valid to WR High Hold Time
NOTES The timing is measured with a load of 50 pF on SCLK and DRDY. SCLK can be operated with a load capacitance of 50 pF maximum. 1 Sample tested at +25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 All digital outputs are timed with the load circuit below and, except for t 2, are defined as the time required for an output to cross 0.8 V or 2 V, whichever occurs last. 3 The AD7721 is production tested with f CLK at 10 MHz for parallel mode operation and at 15 MHz for serial mode operation. However, it is guaranteed by characterization to operate with CLK frequencies down to 100 kHz. 4 t2 is the time from RFS crossing 1.6 V to SCLK crossing 0.8 V. 5 t8 and t15 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit shown below. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitance.
1.6mA
IOL
TO OUTPUT PIN
+1.6V CL 50pF IOH
200 A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
-4-
REV. A
AD7721
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise stated)
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital Input Voltage to DGND . . . -0.3 V to DVDD + 0.3 V Analog Input Voltage to AGND . . . . -0.3 V to AVDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . 10 mA Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (S Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +150C Plastic Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 74C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . Cerdip Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . Lead Temperature, Soldering (10 sec) . . . . . . . . . . SOIC Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .
+260C 51C/W +300C 72C/W +215C +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latchup.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
PIN CONFIGURATION
Model AD7721AN AD7721AR AD7721SQ
Temperature Range -40C to +85C -40C to +85C -55C to +125C
Package Option* N-28 R-28 Q-28
SCLK/DB7 1 DB8 2 DB9 3 RFS/DB10 4 SDATA/DB11 5 DGND 6 28 DB6 27 RD 26 WR 25 DVAL/SYNC 24 AGND
*N = Plastic DIP; R = 0.3" Small Outline IC (SOIC); Q = Cerdip.
AD7721
TOP VIEW 23 VIN2 DSUBST 7 (Not to Scale) 22 VIN1 DGND 8 STBY/DB0 9 DVDD 10 CAL/DB1 11 UNI/DB2 12 DB3 13 DB4 14 21 REFIN 20 AGND 19 AVDD 18 CS 17 CLK 16 DRDY 15 SYNC/DB5
REV. A
-5-
AD7721
PIN FUNCTION DESCRIPTIONS
Mnemonic AVDD AGND DVDD DGND DSUBST VIN1 VIN2 REFIN
Function Analog Positive Supply Voltage, +5 V 5%. Ground reference point for analog circuitry. Digital Supply Voltage, +5 V 5%. Ground reference point for digital circuitry. DGND must be connected via its own short path to AGND (Pin 24). This is the substrate connection for digital circuits. It must be connected via its own short path to AGND (Pin 24). Analog Input. In unipolar operation, the analog input range on VIN1 is VIN2 to (VIN2 + VREFIN); for bipolar operation, the analog input range on VIN1 is (VIN2 VREFIN/2). The absolute analog input range must lie between 0 and AVDD. The analog input is continuously sampled and processed by the analog modulator. Reference Input. The AD7721 operates with an external reference, of value 2.5 V nominal. A suitable reference for operation with the AD7721 is the AD780. A 100 nF decoupling capacitor is required between REFIN and AGND. CMOS Logic Clock Input. The AD7721 operates with an external clock which is connected to the CLK pin. The modulator samples the analog input on both phases of the clock, increasing the sampling rate to 20 MHz (CLK = 10 MHz) or 30 MHz (CLK = 15 MHz).
CLK
Serial Mode Only
CS, RD, WR
DRDY SDATA/DB11
RFS/DB10 DB9 DB8 SCLK/DB7 DB6 SYNC/DB5 DB4 DB3 UNI/DB2 CAL/DB1 STBY/DB0 DVAL/SYNC
To select the serial interface mode of operation, the AD7721 must be powered up with CS, RD and WR all tied to DGND. After two clock cycles, the AD7721 switches into serial mode. These pins must remain low during serial operation. In the serial interface mode, a rising edge on DRDY indicates that new data is available to be read from the interface. During a synchronization or calibration cycle, DRDY remains low until valid data is available. Serial Data Output. Output serial data becomes active after RFS goes low. Sixteen bits of data are clocked out starting with the MSB. Serial data is clocked out on the rising edge of SCLK and is valid on the subsequent falling edge of SCLK. Receive Frame Synchronization. Active low logic input. This is a logic input with RFS provided by connecting this input to DRDY. When RFS is high, SDATA is high impedance. This is a test mode pin. This pin must be tied to DGND. This is a test mode pin. This pin must be tied to DGND. Serial Clock. Logic Output. The internal digital clock is provided as an output on this pin. Data is output from the AD7721 on the rising edge of SCLK and is valid on the falling edge of SCLK. This is a test mode pin. This pin must be tied to DGND. Synchronization Logic Input. A rising edge on SYNC starts the synchronization cycle. SYNC must be pulsed low for at least one clock cycle to initiate a synchronization cycle. This is a test mode pin. This pin must be tied to DGND. This is a test mode pin. This pin must be tied to DGND. Analog Input Range Select, Logic Input. A logic low on this input selects unipolar mode. A logic high selects bipolar mode. Calibration Mode Logic Input. CAL must go high for at least one clock cycle to initiate a calibration cycle. Standby Mode Logic Input. A logic high on this pin selects standby mode. Data Valid Digital Output. In serial mode, this pin is a dedicated data valid pin.
-6-
REV. A
AD7721
Parallel Mode Only
Mnemonic CS RD WR DRDY DVAL/SYNC
Function Chip Select Logic Input. Read Logic Input. This digital input is used in conjunction with CS to read data from the device. Write Logic Input. This digital input is used in conjunction with CS to write data to the control register. In parallel interface mode, a falling edge on DRDY indicates that new data is available to be read from the interface. During a synchronization or calibration cycle, DRDY remains high until valid data is available. The function of this pin is determined by the state of bit DB3 in the control register. Writing a logic zero to bit DB3 will program this pin to be a DVAL output. Writing a logic one to bit DB3 will program this pin to be a SYNC input pin. A rising edge on SYNC starts the synchronization cycle. SYNC must be pulsed low for at least one clock cycle. When switching this pin from SYNC mode to DVAL mode, it is important that there are no rising edges on the pin which could cause resynchronization. For this purpose, an internal pull-up resistor has been included on this pin. Thus, when the external driver driving this pin in SYNC mode is switched off, the DVAL/SYNC pin remains high. These pins are both data outputs and control register inputs. Output data is placed on these pins by taking RD and CS low. Data on these pins is read into the control register by toggling WR low with CS low. With RD high, these pins are high impedance.
SDATA/DB11- STBY/DB0
Control functions such as CAL, UNI and STBY, which are available as pins in serial mode, are available as bits in parallel mode. Table I lists the contents of the control register onboard the AD7721. This register is written to in parallel mode using the WR pin.
Table I. Function of Control Register Bits Control Register Bit Function DB0 DB1 STBY CAL
Logical State 0 1 0 1
Mode Normal Operation. Power-Down (Standby) Mode. Normal Operation. Writing a Logic "1" to this bit starts a calibration cycle. Internal logic resets this bit to zero at the end of calibration.
DB2
DB3 DB9
UNI
DVAL/SYNC
0
1 0 1 0
Unipolar Mode.
Bipolar Mode. Sets DVAL/SYNC Pin to DVAL Mode. Sets DVAL/SYNC Pin to SYNC Mode. This bit is used for testing the AD7721. A logic low MUST be written into this bit for normal operation.
REV. A
-7-
AD7721
TERMINOLOGY Integral Nonlinearity
This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 LSB below the first code transition (100 . . . 00 to 100 . . . 01 in bipolar mode and 000 . . . 00 to 000 . . . 01 in unipolar mode) and full scale, a point 0.5 LSB above the last code transition (011 . . . 10 to 011 . . . 11 in bipolar mode and 111 . . . 10 to 111 . . . 11 in unipolar mode). The error is expressed in LSBs.
Differential Nonlinearity
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic.
USING THE AD7721 ADC Differential Inputs
This is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the ADC.
Common Mode Rejection Ratio
The AD7721 uses differential inputs to provide common-mode noise rejection. In the bipolar mode configuration, the analog input range is 1.25 V. The designed code transitions occur midway between successive integer LSB values. The output code is 2s complement binary with 1 LSB = 0.61 mV in parallel mode and 38 V in serial mode. The ideal input/output transfer function is illustrated in Figure 2. In the unipolar mode, the analog input range is 0 V to 2.5 V. Again, the designed code transitions occur midway between successive integer LSB values. The output code is straight binary with 1 LSB = 0.61 mV in parallel mode and 38 V in serial mode. The ideal input/output transfer function is shown in Figure 3.
OUTPUT CODE 011...111 011...110
The ability of a device to reject the effect of a voltage applied to both input terminals simultaneously--often through variation of a ground level--is specified as a common-mode rejection ratio. CMRR is the ratio of gain for the differential signal to the gain for the common-mode signal.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition from the ideal VIN1 voltage which is (VIN2 + 0.5 LSB) when operating in the unipolar mode.
Bipolar Offset Error
AD7721
000...010 000...001 000...000 111...111 111...110 -REF IN/2 +REF IN/2-1LSB
This is the deviation of the midscale transition (111 . . . 11 to 000 . . . 00) from the ideal VIN1 voltage which is (VIN2 - 0.5 LSB) when operating in the bipolar mode.
Unipolar Full-Scale Error
Unipolar full-scale error is the deviation of the last code transition (111 . . . 10 to 111 . . . 11) from the ideal VIN1 voltage which is (VIN2 + VREFIN - 3/2 LSBs).
Bipolar Full-Scale Error
100...001 100...000 0V DIFFERENTIAL INPUT VOLTAGE (VIN1-VIN2)
The bipolar full-scale error refers to the positive full-scale error and the negative full-scale error. The positive full-scale error is the deviation of the last code transition (011 . . . 10 to 011 . . . 11) from the ideal VIN1 voltage which is (VIN2 + VREFIN/2 - 3/2 LSB). The negative full-scale error is the deviation of the first code transition (100 . . . 00 to 100 . . . 01) from the ideal VIN1 voltage which is (VIN2 - VREFIN/2 + 0.5 LSB).
Signal to (Noise + Distortion)
Figure 2. AD7721 Bipolar Mode Transfer Function
OUTPUT CODE
Signal to (Noise + Distortion) is measured signal to noise at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fCLK/2) but excluding the dc component. Signal to (Noise + Distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio for a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB where N is the number of bits. Thus, for an ideal 12-bit converter, Signal to (Noise + Distortion) = 74 dB.
Total Harmonic Distortion
111...111 111...110 111...101 111...100
AD7721
000...011 000...010 000...001 000...000 0V REF IN-1LSB DIFFERENTIAL INPUT VOLTAGE (VIN1-VIN2)
Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD7721, THD is defined as THD = 20 log (V 2 + V 3 + V 4 + V 5 + V 6 ) V1 -8-
2 2 2 2 2
Figure 3. AD7721 Unipolar Mode Transfer Function
REV. A
AD7721
Input Circuits
The purpose of antialiasing filters is to attenuate out of band signals that would otherwise be mixed down into the signal band. With traditional ADCs, high order filters using expensive high tolerance passive components are often required to perform this function. Using oversampling, as employed on the AD7721, this problem is considerably alleviated. Figure 4a shows the digital filter frequency response. Due to the sampling nature of the digital filter, the passband is repeated about the operating clock frequency and at multiples of the clock frequency. Out of band signals coincident with any of the filter images are mixed down into the passband. Figure 4b shows the frequency response of the antialias filter required to provide a particular level of attenuation at the first image frequency. Figure 4c shows the frequency response of the antialias filter required to achieve the same level of attenuation with a traditional ADC. The much smaller transition band can only be achieved with a very high order filter.
The choice of the filter corner frequency will depend on the amount of rolloff which is acceptable in-band and the attenuation which is required at the first image frequency. For example, when fCLK = 15 MHz, REXT = 50 , CEXT = 7.84 nF, the inband rolloff is 1 dB and the attenuation at the first image frequency is 31.1 dB. Increasing the size of the external resistor above 50 can cause increased distortion due to nonlinear charging currents.
REXT VIN1 ANALOG INPUT REXT VIN2 CEXT CEXT
AD7721
Figure 5. Simple RC Antialiasing Filter
0dB
fCLK
2fCLK
3fCLK
a. Digital Filter Frequency Response
OUTPUT DATA RATE 0dB ANTIALIAS FILTER RESPONSE REQUIRED ATTENUATION
Figure 6 shows a simple circuit that can be used to drive the AD7721 in unipolar mode. The input of the AD7721 is sampled by a 1.6 pF input capacitor. This creates glitches on the input of the modulator. By placing the RC filter directly before the AD7721, rather than before the operational amplifier, these glitches are prevented from being fed back into the operational amplifier and creating distortion. The resistor in this diagram, as well as creating a pole for the antialias filter, also isolates the storage capacitor from the operational amplifier which may otherwise be unstable.
ANALOG INPUT REXT VIN1 CEXT
fCLK
COMMON MODE VOLTAGE
AD7721
VIN2
b. Frequency Response of Antialias Filter (AD7721)
ANTIALIAS FILTER RESPONSE OUTPUT DATA RATE REQUIRED ATTENUATION
Figure 6. Antialiasing Circuits
0dB
c. Frequency Response of Antialias Filter (Traditional ADC) Figure 4. Frequency Response of Antialiasing Filters
A suitable operational amplifier is the AD847 if a 15 V power supply is available. If only a +5 V power supply is available, the AD820 can be used. This operational amplifier can be used with input bandwidths up to 80 kHz. However, the slew rate of this operational amplifier limits its performance to 80 kHz. Above this frequency, the performance of the AD820 degrades. For both filters, the capacitor CEXT should have a low temperature coefficient and should be linear to avoid distortion. Polypropylene or polystyrene capacitors are suitable.
Offset and Gain Calibration
Figure 5 shows a simple antialiasing filter which can be used with the AD7721. The -3 dB corner frequency (f3 dB) of the antialias filter is given by Equation 1, and the attenuation of the filter is given by Equation 2. Attenuation at the first image frequency is given by Equation 3. f3 dB = 1/(2 REXT CEXT) Equation 1
Attenuation = 20 log 1 / 1 + ( f / f 3 dB
Attenuation (First Image) = 2 20log 1/ 1+ 0.986 fCLK / f 3dB
)2
Equation 2
A calibration of offset and gain errors can be performed in both serial and parallel modes by initiating a calibration cycle. During this cycle, offset and gain registers in the filter are loaded with values representing the dc offset of the analog modulator and a modulator gain correction factor. In normal operation, the offset register is subtracted from the digital filter output and this result is then multiplied by the gain correction factor to obtain an offset and gain corrected final result. During the calibration cycle, in which the offset of the analog modulator is evaluated, the inputs to the modulator are shorted together internally. When the modulator and digital filter settle, the average of 8 output results is calculated and stored in the offset register. The gain of the modulator is determined by -9-
(
)
Equation 3
REV. A
AD7721
switching the positive input of the modulator to the reference voltage and the negative input to AGND. Again, when the modulator and digital filter settle, a gain correction factor is calculated from the average of 8 output results and stored in the gain register. After the calibration registers have been loaded with new values, the inputs of the modulator are switched back to the input pins. However, correct data is available at the interface only after the modulator and filter have settled to the new input values. The whole calibration cycle is controlled by internal logic, and the controller need only initiate the cycle. The calibration values loaded into the registers only apply for the particular analog input mode (bipolar/unipolar) selected when initiating the calibration cycle. On changing to a different analog input mode, a new calibration must be performed. The duration of the calibration cycle is up to 6720 clock cycles for the unipolar mode and up to 9024 clock cycles for the bipolar mode. Until valid data is available at the interface, the DRDY pin remains high in parallel mode and low in serial mode. Should the part see a rising edge on the SYNC pin in serial mode or on the DVAL/SYNC pin (if programmed as a SYNC pin), then the calibration cycle is discontinued and a synchronization operation will be performed. Similarly, putting the part into standby mode during the cycle will discontinue the calibration cycle. The calibration registers are static and retain their contents even during standby. They need to be updated only if unacceptable drifts in analog offsets or gain are expected. On power-up in parallel mode, the offset and gain errors may contain incorrect values and therefore a calibration must be performed at least once after power-up. In serial mode, a calibration on power-up is not mandatory if the CAL pin is grounded prior to power-up as the calibration register will be reset to zero. Before initiating a calibration routine, ensure that the supplies have settled and that the voltage on the analog input pins is between the supply voltages. Calibration does not affect the synchronization of the part.
Synchronization Standby
The part can be put into a low power standby mode by writing to the configuration register in parallel mode or by taking the STBY pin high in serial mode. During Standby, the clock to both the modulator and the digital filter is turned off and bias is removed from all analog circuits. On coming out of standby mode, the DRDY pin remains high in parallel mode and low in serial mode for 2080 clock cycles. When DRDY changes state, valid data is available at the interface. As soon as the part is taken out of standby mode, a synchronization or calibration cycle can be initiated.
DVAL
The DVAL pin or the DVAL/SYNC pin, when programmed as a DVAL pin, is used to indicate that an overrange input signal has resulted in invalid data at the ADC output. Small overloads will result in DVAL going low and the output being clipped to positive or negative full scale, depending on the sign of the overload. As with all single bit DAC high order sigma-delta modulators, large overloads on the inputs can cause the modulator to go unstable. The modulator is designed to be stable with signals within the input bandwidth that exceed full scale by 20%. When instability is detected by internal circuits, the modulator is reset to a stable state and DVAL is held low for 2080 clock cycles. During this period, the output registers are set to negative full scale. Whenever DVAL goes low, DRDY will continue to indicate that there is data to be read.
Varying the Master Clock Frequency
The AD7721 can be operated with clock frequencies less than 10 MHz. The sample rate, output word rate and cutoff frequency of the FIR filters are directly proportional to the master clock frequency. The analog input is sampled at a frequency of 2 fCLK while the output word rate equals fCLK/32. For example, reducing the clock frequency to 5 MHz leads to a sample frequency of 10 MHz, an output word rate of 156.25 kHz and a corner frequency of 76.4 kHz. The AD7721 can be operated with clock frequencies down to 100 kHz.
Power Supply Sequencing
Data is presented at the interface at 1/32 the CLK frequency. In order that this data is presented to the interface at a known point in time or to ensure that the data from more than one device is a filtered and decimated result derived from the same input samples, a synchronizing function has been provided. In parallel mode, the DVAL/SYNC pin must first be configured as a SYNC pin by writing to the control register. In serial mode, there is a dedicated SYNC pin. On the rising edge of the SYNC pulse or the DVAL/SYNC pulse, the digital filter is reset to a known state. For 2080 clock cycles, DRDY remains high in parallel mode and low in serial mode. When DRDY changes state at the end of this period, valid data is available at the interface. Synchronizing the part has no affect on the values in the calibration register. SYNC is latched internally on the rising edge of DCLK which is a delayed version of the clock on the CLK pin. Should SYNC go high coincidentally with DCLK, there is a potential uncertainty of one clock cycle in the start of the synchronization cycle. To avoid this, SYNC should be taken high after the falling edge of the clock on the CLK pin and before the rising edge of this clock.
If separate analog and digital supplies are used, care must be taken to ensure that both supplies remain within 0.3 V of each other both during normal operation and during power-up and power-down to completely eliminate the possibility of latch-up. If this cannot be assured, then the protection circuit shown in Figure 7 is recommended. The 10 resistors may be required to limit the current through the diodes if particularly fast edges are expected on the supplies during power-up and power-down. If only one supply is available, then DVDD must be connected to the analog supply. Supply decoupling capacitors are still required as close as possible to both supply pins.
IN4148
10 IN4148 1F 10nF AVDD DVDD 10nF
10 1F
AD7721
Figure 7. Powering-Up Protection Scheme
-10-
REV. A
AD7721
CIRCUIT DESCRIPTION Sigma-Delta ADC
a linear phase response. This is very difficult to achieve with analog filters. Analog filters, however, can remove noise superimposed on the signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals, near full-scale, have the potential to overload the analog modulator even though the average value of the signal is within limits.
The AD7721 ADC employs a sigma-delta conversion technique that converts the analog input into a digital pulse train. Due to the high oversampling rate, which spreads the quantization noise from 0 to fCLK/2, the noise energy which is contained in the band of interest is reduced (Figure 8a). To reduce the quantization noise further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (Figure 8b). The digital filter that follows the modulator removes the large out of band quantization noise (Figure 8c), while converting the digital pulse train into parallel 12 bit wide binary data or serial 16 bit wide binary data.
0.0
GAIN - dB
-50.0
-100.0
QUANTIZATION NOISE BAND OF INTEREST
fCLK/ 2
-150.0 0.0fCLK
0.1fCLK
0.2fCLK
0.3fCLK
0.4fCLK
0.5fCLK
FREQUENCY
a. Figure 9a. 128 Tap FIR Filter Frequency Response
NOISE SHAPING
0.0
BAND OF INTEREST
fCLK/ 2
GAIN - dB -50.0
b.
DIGITAL FILTER CUTOFF FREQUENCY WHICH EQUALS 152.8kHz (10MHz) OR 229.2kHz (15MHz)
-100.0
BAND OF INTEREST
fCLK/ 2
-150.0 0.0fCLK/32 0.2fCLK/32 0.4fCLK/32
0.6fCLK/32 0.8fCLK/32 1.0fCLK/32
FREQUENCY
c. Figure 8. Sigma-Delta ADC
Digital Filter
Figure 9b. 83 Tap FIR Filter Frequency Response
SERIAL INTERFACE
The digital filter that follows the modulator removes the large out of band quantization noise, while converting the one bit digital pulse train into 12-bit or 16-bit wide binary data. The digital filter also reduces the data rate from fCLK at the input of the filter to fCLK/32 at the output of the filter. The output data rate is a little over twice the signal bandwidth which guarantees that there is no loss of data in the signal band. The AD7721 employs 2 FIR filters in series. The first filter is a 128 tap filter that samples the output of the modulator at fCLK. The second filter is an 83 tap half-band filter that samples the output of the first filter at fCLK/16 and decimates by 2. The frequency response of the 2 filters is shown in Figure 9. Digital filtering has certain advantages over analog filtering. First, since digital filtering occurs after the A/D conversion, it can remove noise injected during the conversion process. Analog filtering cannot do this. Second, the digital filter combines low passband ripple with a steep roll off, while also maintaining REV. A
The AD7721's serial communication port allows easy interfacing to industry-standard microprocessors, microcontrollers and digital signal processors. The AD7721 is operated in selfclocking mode, the AD7721 providing the serial clock. The RFS signal is also provided by the AD7721 by tying RFS to DRDY. Figure 10 shows the timing diagram for reading from the AD7721. DRDY goes high to indicate that a conversion has been completed. DRDY remains high for one internal clock (15 MHz) cycle and then goes low for the next 31 clock cycles. New data is loaded into the output shift register on the rising edge of DRDY. When DRDY goes low, the data is accessed from the AD7721. Although the AD7721 has a 12-bit digital output in the parallel mode, sixteen bits of data are available for transmission in the serial mode, starting with the MSB. Serial data is clocked out of the device on the rising edge of SCLK and is valid on the falling edge of SCLK. -11-
AD7721
PARALLEL INTERFACE Read Operation Write Operation
The device defaults to parallel mode if CS, RD and WR are not tied to DGND together. Figure 11 shows a timing diagram for reading from the AD7721 in the parallel mode. When operating the device in parallel mode, CS and RD should be tied to DGND permanently except when control information is being written to the AD7721. DRDY goes high for 2 clock cycles to indicate that new data is available from the interface. The AD7721 outputs this data after the falling edge of DRDY. This DRDY pin can be used to drive an edge-triggered interrupt of a microprocessor.
The write operation is used to write data into the control register. The outputs of the control register select the analog input range, allow the part to be put into power-down (standby) mode, define the function of the DVAL/SYNC pin, and initiate the calibration routine. After power-up and after at least 16 clock cycles, the control register must be written to. A calibration must also be performed at least once after power-up to set the calibration registers. The function of each bit in the control register is shown in Table I. When writing to the control register, the RD pin must be taken high so that the pins D0 to D11 are configured as inputs.
t1
RFS (I) / DRDY (O)
t9
t2
SCLK (O)
t4 t5
DB15 DB14 DB13 DB12 DB11 DB10
t3
DATA OUT (O)
t6
DB0
t7
t8
NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
Figure 10. Serial Mode Output Register Read
CS (I) RD (I)
t10
DRDY (O)
t12 t11
DB0-DB11 (O) NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.
Figure 11. Parallel Mode Output Register Read
CS (I)
t13
WR (I)
t14
DB0-DB11 (I) NOTE: (I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. VALID DATA
t15
Figure 12. Write Timing Diagram
-12-
REV. A
AD7721
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7721 has a variety of interfacing options. It offers two operating modes--serial and parallel.
Serial Interfacing
In serial mode, the AD7721 can be directly interfaced to several DSPs. In all cases, the AD7721 operates as the master with the DSP acting as the slave. The AD7721 provides its own serial clock to clock the digital word from the AD7721 to the DSP. The serial clock is a buffered version of the master clock CLK. The frame synchronization signal to the AD7721 and the DSP is provided by the DRDY signal. Because the serial clock from the AD7721 has the same frequency as the master clock, DSPs that can accept high serial clock frequencies are required. When the AD7721 is being operated with a 15 MHz clock, Analog Devices' ADSP-2106x SHARC(R) DSP is suitable as this DSP can accept very high serial clocks. The 40 MHz version of this DSP can accept a serial clock of 40 MHz maximum. To interface the AD7721 to other DSPs, the master clock frequency of the AD7721 can be reduced so that it equals the maximum allowable frequency of the serial clock for the DSP. This will cause the sampling rate, the output word rate and the bandwidth of the AD7721 to be reduced by a proportional amount. The ADSP-21xx family can operate with a maximum serial clock of 13.824 MHz, the DSP56002 uses a maximum serial clock of 13.3 MHz while the TMS320C5x-57 accepts a maximum serial clock of 10.989 MHz. When the AD7721 is being operated with a low master clock frequency (< 8 MHz), DSPs such as the TMS320C20/C25 and DSP56000/1 can be used. Figures 13 to 15 show the interfaces between the AD7721 and several DSPs. In all cases, CS, RD and WR are permanently hardwired to DGND.
AD7721 to ADSP-21xx Interface
SENDN = 0 (the MSB of the 16-bit word will be received by the DSP first), ICLK = 0 (an external serial clock will be used), RFSR = 0 (a frame sync is required for every word transfer), IRFS = 0 (the receive frame sync signal is external), CKRE = 0 (the receive data will be latched into the DSP on the falling clock edge), LAFS = 0 (the DSP begins reading the 16 bit word after the DSP has identified the frame sync signal rather than the DSP reading the word at the same instant as the frame sync signal has been identified), LRFS = 0 (RFS is active high).
AD7721 to DSP56002 Interface
Figure 14 shows the AD7721 to DSP56002 interface. If the AD7721 is being used at a lower clock frequency (5.128 MHz), the DSP56000 or DSP56001 can be used. The interface will be similar for all three DSPs. To interface the DSP56002 to the AD7721, the DSP56002 is configured as follows: SYN = 1 (synchronous mode), SCD1 = 0 (RFS will be an input), GCK = 0 (a continuous clock will be used), SCKD = 0 (the serial clock will be external), WL1 = 1, WL0 = 0 (transfers will be 16 bits wide), FSL1 = 0, FSL0 = 1 (the frame sync will be active at the beginning of each transfer).
DSP56002
IRQ
AD7721
DRDY RFS WR RD CS
SRD SC1 SCK
SDATA SCLK
Figure 14. AD7721 to DSP56002 Interface
Several of the ADSP-21xx family can interface directly to the AD7721. DRDY is used as the frame sync signal for both the ADSP-21xx and the AD7721. DRDY, which goes high for two clock cycles when a conversion is complete, can also be used as an interrupt signal if required. Figure 13 shows the AD7721 interface to the ADSP-21xx. For the ADSP-21xx, the bits in the serial port control register should be set up as RFSR = 1 (a frame sync is needed for each transfer), SLEN = 15 (16 bit word lengths), RFSW = 0 (normal framing mode for receive operations), INVRFS = 0 (active high RFS), IRFS = 0 (external RFS), and ISCLK = 0 (external serial clock).
ADSP-21xx
IRQ
Alternatively, the DSP56002 can be operated in asynchronous mode (SYN = 0). In this mode, the serial clock for the Receive section in inputted to the SC0 pin. This is accomplished by setting bit SCD0 to 0 (external Rx clock).
AD7721 to TMS320C20/C25/C5x Interface
AD7721
DRDY RFS WR RD CS
Figure 15 shows the AD7721 to TMS320C20/C25/C5x interface. For the TMS320C5x, FSR and CLKR are automatically configured as inputs. The serial port is configured as follows: FO = 0 (16-bit word transfers), FSM = 1 (a frame sync occurs for each transfer). Figure 15 shows the interface diagram when the AD7721 is being interfaced to the TMS320C20 and the TMS320C25 also but, these DSPs can be used only when the AD7721 is being used at a lower frequency such as 5 MHz (C25) or 2.56 MHz (C20).
AD7721
INT0 DRDY RFS WR RD CS DR FSR CLKR SDATA SCLK
DR RFS SCLK
SDATA SCLK
TMS320C 20/25/5x
Figure 13. AD7721 to ADSP-21xx Interface
The interface between the AD7721 and the ADSP-2106x SHARC DSP is the same as shown in Figure 13, but the DSP is configured as follows: SLEN = 15 (16-bit word transfers),
SHARC is a registered trademark of Analog Devices, Inc.
Figure 15. AD7721 to TMS320C20/25/5x Interface
REV. A
-13-
AD7721
Parallel Interface
In parallel mode, the DRDY signal is still available. This signal can be used to generate an interrupt in the DSP as DRDY goes high for two clock cycles when a conversion is complete. Data is available from the AD7721 every 32 CLK cycles. The ADC outputs the 12-bit digital word automatically. Hence, latches are needed into which the 12-bit parallel word can be transferred. Because RD and CS are permanently tied to DGND when the ADC is performing A-to-D conversions, some further glue logic is needed to interface the AD7721 to a DSP in parallel mode. When a digital word is available from the AD7721, it will be automatically transferred to the latches. The DRDY signal informs the DSP that a new word is available to be read. The DSP then reads the word from the latches. By using the latches, the microprocessor is free to perform other tasks between reads from the AD7721. When using the parallel mode, CS and RD should be permanently tied to DGND, RD being taken high only when a control word is being written to the AD7721. CS and RD should not be pulsed, as is the procedure with other ADCs, as the specifications for the device will degrade and the part may become unstable.
DSP
INTERRUPT WR RD DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 1Y1 1G 2G 1A1 1Y2 1A2 1Y3 1A3 1Y4 HC244 1A4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 CS DECODE
DMA13-DMA0
DMS IRQ
EN ADDR DECODE CS
AD7721
DRDY WR RD
WR RD 1Y1 1G 2G 1A1 1Y2 1A2 1Y3 1A3 1Y4 HC244 1A4 2Y1 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4
DMD11-DMD
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
ADSP-21xx
1Y1 1G 2G 1A1 1Y2 1A2 1Y3 1A3 1Y4 HC244 1A4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4
DB3 DB2 DB1 DB0
CS
Figure 17. AD7721 to ADSP-21xx Interface
AD7721 to DSP56002 Interface
AD7721
DRDY WR RD DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
Figure 18 shows the AD7721 to DSP56002 interface. The connections for the DSP56002 are similar to those for the ADSP-21xx family. The diagram shows the connections for the DSP56002, but the connections for the DSP56000 and DSP56001 are similar.
A15-A0
DS IRQ
EN ADDR DECODE CS
AD7721
DRDY WR RD
DB3 DB2 DB1 DB0
1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2A1 2A2 2A3 2A4
1A1 1A2 1A3 1A4 2Y1 2Y2 2Y3 2Y4
DB3 DB2 DB1 DB0
WR RD
CS
Figure 16. Interfacing the AD7721 to a Microprocessor in Parallel Mode
AD7721 to ADSP-21xx Interface
D11-D0
1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2Y1 2Y2 2Y3 2Y4
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
Figure 17 shows the AD7721 to ADSP-21xx interface. DRDY is used to interrupt the DSP when a conversion is complete and the HC244 latches contain a new word. The WR signal from the DSP is used to drive both the RD and WR inputs of the AD7721 since RD will be tied low at all times except when the control register of the device is being written to. The RD signal of the DSP is used to enable the outputs of the latches so that the 12 bit word can be read into the DSP. Two 8-bit latches are used. Twelve of the latches are used to hold the 12-bit conversion from the AD7721. The remaining four latches are used to hold the control information being transferred from the DSP to the AD7721. When a control word is being written to the AD7721, Bits 4 to 6 and Bits 9 to 10, which are test bits, need to be loaded with zeros. Therefore, pull-down resistors are used so that Pins 4 to 6 and 9 to 10 are tied to ground when the control register is being loaded.
DSP56002
1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2A1 2A2 2A3 2A4
1A1 1A2 1A3 1A4 2Y1 2Y2 2Y3 2Y4
DB3 DB2 DB1 DB0
CS
Figure 18. AD7721 to DSP56002 Interface
AD7721 to TMS320C20/C25/C5x Interface
Figure 19 shows the AD7721 to TMS320C20/C25 interface while Figure 20 shows the AD7721 to TMS320C5x interface. Again, the interface is similar to that of the ADSP-21xx. However, the TMS320C20/C25 has a common RD/W pin. This output is decoded using the STRB pin. The TMS320C5x has a RD/W pin also so external glue logic can be used to decode the RD/W pin as done for the C20 and C25. An alternative is to use the RD and WE pins of the C5x. Using these outputs, WE operates as the WR signal while RD functions as the RD signal. Also, additional glue logic is not required.
-14-
REV. A
AD7721
A15-A0
AD7721
IS IRQ STRB RD/W EN ADDR DECODE CS DRDY WR RD 1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2Y1 2Y2 2Y3 2Y4 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
power supplies, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog inputs provided the noise source does not saturate the analog modulator. As a result, the AD7721 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7721 is high and the noise levels from the AD7721 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7721 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD7721 is the only device requiring an AGND to DGND connection, the ground planes should be connected at the AGND and DGND pins of the AD7721. DSUBST, which is the substrate connection for the digital circuitry of the AD7721, should be connected directly to AGND. If the AD7721 is in a system where multiple devices require AGND to DGND connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7721. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7721 to avoid noise coupling. The power supply lines to the AD7721 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important when using high resolution ADCs. All analog and digital supplies should be decoupled to AGND and DGND respectively with 10 nF ceramic capacitors in parallel with 1 F tantalum capacitors. To achieve the best from these decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7721, it is recommended that the system's AVDD supply is used. This supply should have the recommended analog supply decoupling between the AVDD pin of the AD7721 and AGND and the recommended digital supply decoupling capacitor between the DVDD pins and DGND.
D11-D0
TMS320C20/ C25
1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2A1 2A2 2A3 2A4
1A1 1A2 1A3 1A4 2Y1 2Y2 2Y3 2Y4
DB3 DB2 DB1 DB0
CS
Figure 19. AD7721 to TMS320C20/C25 Interface
DMA13-DMA0
IS IRQ WE RD
EN ADDR DECODE CS
AD7721
DRDY WR RD
DMD11-DMD
1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2Y1 2Y2 2Y3 2Y4
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
TMS320C5x
1Y1 1G 2G 1Y2 1Y3 1Y4 HC244 2A1 2A2 2A3 2A4
1A1 1A2 1A3 1A4 2Y1 2Y2 2Y3 2Y4
DB3 DB2 DB1 DB0
CS
Figure 20. AD7721 to TMS320C5x Interface
Grounding and Layout
Since the analog inputs are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part will remove common-mode noise on these inputs. The analog and digital supplies to the AD7721 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. The digital filter will provide rejection of broadband noise on the
REV. A
-15-
AD7721
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-28)
1.565 (39.70) 1.380 (35.10)
28 15
0.580 (14.73) 0.485 (12.32)
1 14
PIN 1 0.250 (6.35) MAX 0.200 (5.05) 0.022 (0.558) 0.125 (3.18) 0.014 (0.356)
0.060 (1.52) 0.015 (0.38)
0.625 (15.87) 0.600 (15.24)
0.195 (4.95) 0.125 (3.18)
0.150 (3.81) MIN 0.100 (2.54) BSC 0.070 (1.77) MAX SEATING PLANE
0.015 (0.381) 0.008 (0.204)
SOIC (R-28)
0.7125 (18.10) 0.6969 (17.70)
28 15
1
14
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.4193 (10.65) 0.3937 (10.00)
0.2992 (7.60) 0.2914 (7.40)
0.0291 (0.74) x 45 0.0098 (0.25)
0.0118 (0.30) 0.0040 (0.10)
0.0500 (1.27) BSC
8 0.0192 (0.49) 0 SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
Cerdip (Q-28)
0.005 (0.13) MIN
28
0.100 (2.54) MAX
15
0.610 (15.49) 0.500 (12.70)
1 14
PIN 1 1.490 (37.85) MAX 0.225 (5.72) MAX 0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.125 (3.18) 0.014 (0.36) 0.090 (2.29) 0.015 (0.38) MIN 0.150 (3.81) MIN 0.070 (1.78) SEATING 0.030 (0.76) PLANE 15 0
0.620 (15.75) 0.590 (14.99)
0.018 (0.46) 0.008 (0.20)
-16-
REV. A
PRINTED IN U.S.A.
C2094a-2-12/97

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